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INTEGRATED CIRCUITS
DATA SHEET
74AHC2G00; 74AHCT2G00 2-input NAND gate
Product specification 2004 Jan 21
Philips Semiconductors
Product specification
2-input NAND gate
FEATURES * Symmetrical output impedance * High noise immunity * ESD protection: - HBM EIA/JESD22-A114-A exceeds 2000 V - MM EIA/JESD22-A115-A exceeds 200 V - CDM EIA/JESD22-C101 exceeds 500 V. * Low power dissipation * Balanced propagation delays * SOT505-2 and SOT765-1 package * Specified from -40 to +85 C and -40 to +125 C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 3.0 ns.
74AHC2G00; 74AHCT2G00
DESCRIPTION The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS device. The 74AHC2G/AHCT2G00 provides the 2-input NAND gate function.
TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. PARAMETER propagation delay nA and nB to nY input capacitance power dissipation capacitance per gate CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC2G CL = 15 pF; VCC = 5 V 3.5 1.5 17 AHCT2G 3.6 1.5 18 ns pF pF UNIT
2004 Jan 21
2
Philips Semiconductors
Product specification
2-input NAND gate
FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION nB L H L H
74AHC2G00; 74AHCT2G00
OUTPUT nY H H H L
PACKAGE TYPE NUMBER 74AHC2G00DP 74AHCT2G00DP 74AHC2G00DC 74AHCT2G00DC PINNING PIN 1 2 3 4 5 6 7 8 1A 1B 2Y GND 2A 2B 1Y VCC SYMBOL data input data input data output ground (0 V) data input data input data output supply voltage DESCRIPTION TEMPERATURE RANGE -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C PINS 8 8 8 8 PACKAGE MATERIAL TSSOP8 TSSOP8 VSSOP8 VSSOP8 plastic plastic plastic plastic CODE SOT505-2 SOT505-2 SOT765-1 SOT765-1 MARKING A00 C00 A00 C00
2004 Jan 21
3
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
handbook, halfpage
1A 1 1B 2
8 VCC 7 1Y 2B 2A
handbook, halfpage
1 2 5 6
1A 1B 2A 2B
1Y
7
00
2Y GND 3 4
MNA711
6 5
2Y
3
MNA712
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1 2
&
7
handbook, halfpage
B Y
5 6
&
3
A
MNA099
MNA713
Fig.3 IEC logic symbol.
Fig.4 Logic diagram.
2004 Jan 21
4
Philips Semiconductors
Product specification
2-input NAND gate
RECOMMENDED OPERATING CONDITIONS
74AHC2G00; 74AHCT2G00
74AHC2G00 SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times CONDITIONS MIN. 2.0 0 0 see DC and AC -40 characteristics per device VCC = 3.3 0.3 V VCC = 5 0.5 V - - TYP. 5.0 - - +25 - - MAX. 5.5 5.5 VCC +125 100 20
74AHCT2G00 UNIT MIN. 4.5 0 0 -40 - - TYP. 5.0 - - +25 - - MAX. 5.5 5.5 VCC +125 - 20 V V V C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC, IGND Tstg PD Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. PARAMETER supply voltage input voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation Tamb = -40 to +125 C VI < -0.5 V VO < -0.5 V or VO > VCC + 0.5 V; note 1 -0.5 V < VO < VCC + 0.5 V CONDITIONS MIN. -0.5 -0.5 - - - - -65 - MAX. +7.0 +7.0 -20 20 25 75 +150 250 UNIT V V mA mA mA mA C mW
2004 Jan 21
5
Philips Semiconductors
Product specification
2-input NAND gate
DC CHARACTERISTICS
74AHC2G00; 74AHCT2G00
Type 74AHC2G00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). CONDITIONS SYMBOL Tamb = 25 C VIH HIGH-level input voltage 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage VI = VIH or VIL IO = -50 A IO = -50 A IO = -50 A IO = -4.0 mA IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 A IO = 50 A IO = 50 A IO = 4.0 mA IO = 8.0 mA ILI ICC CI input leakage current quiescent supply current input capacitance VI = VCC or GND VI = VCC or GND; IO = 0 2.0 3.0 4.5 3.0 4.5 5.5 5.5 - - - - - - - - - 0 0 0 - - - - 1.5 0.1 0.1 0.1 0.36 0.36 0.1 10 10 V V V V V A A pF 2.0 3.0 4.5 3.0 4.5 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 - - - - - - - V V V V V 1.5 2.1 3.85 - - - - - - - - - - - - 0.5 0.9 1.65 V V V V V V PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT
2004 Jan 21
6
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C VIH HIGH-level input voltage 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage VI = VIH or VIL IO = -50 A IO = -50 A IO = -50 A IO = -4.0 mA IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 A IO = 50 A IO = 50 A IO = 4.0 mA IO = 8.0 mA ILI ICC CI input leakage current quiescent supply current input capacitance VI = VCC or GND VI = VCC or GND; IO = 0 2.0 3.0 4.5 3.0 4.5 5.5 5.5 - - - - - - - - - - - - - - - - - 0.1 0.1 0.1 0.44 0.44 1.0 10 10 V V V V V A A pF 2.0 3.0 4.5 3.0 4.5 1.9 2.9 4.4 2.48 3.8 - - - - - - - - - - V V V V V 1.5 2.1 3.85 - - - - - - - - - - - - 0.5 0.9 1.65 V V V V V V VCC (V) MIN. TYP. MAX. UNIT
2004 Jan 21
7
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +125 C VIH HIGH-level input voltage 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage VI = VIH or VIL IO = -50 A IO = -50 A IO = -50 A IO = -4.0 mA IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 A IO = 50 A IO = 50 A IO = 4.0 mA IO = 8.0 mA ILI ICC CI input leakage current quiescent supply current input capacitance VI = VCC or GND VI = VCC or GND; IO = 0 2.0 3.0 4.5 3.0 4.5 5.5 5.5 - - - - - - - - - - - - - - - - - 0.1 0.1 0.1 0.55 0.55 2.0 40 10 V V V V V A A pF 2.0 3.0 4.5 3.0 4.5 1.9 2.9 4.4 2.40 3.70 - - - - - - - - - - V V V V V 1.5 2.1 3.85 - - - - - - - - - - - - 0.5 0.9 1.65 V V V V V V VCC (V) MIN. TYP. MAX. UNIT
2004 Jan 21
8
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
Type 74AHCT2G00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). CONDITIONS SYMBOL Tamb = 25 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -50 A IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 A IO = 8.0 mA ILI ICC ICC CI input leakage current quiescent supply current VI = VIH or VIL VI = VCC or GND; IO = 0 4.5 4.5 5.5 5.5 5.5 - - - - - - 0 - - - - 1.5 - - - - - - - - - - 0.1 0.36 0.1 1.0 1.35 10 - 0.8 - - 0.1 0.44 1.0 10 1.5 10 V V A A mA pF 4.5 4.5 4.4 3.94 4.5 - - - V V 4.5 to 5.5 4.5 to 5.5 2.0 - - - - 0.8 V V PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT
additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 input capacitance
Tamb = -40 to +85 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -50 A IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 A IO = 8.0 mA ILI ICC ICC CI input leakage current quiescent supply current VI = VIH or VIL VI = VCC or GND; IO = 0 4.5 4.5 5.5 5.5 5.5 - - - - - - - V V A A mA pF 4.5 4.5 4.4 3.8 V V 4.5 to 5.5 4.5 to 5.5 2.0 - V V
additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 input capacitance
2004 Jan 21
9
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +125 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -50 A IO = -8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 A IO = 8.0 mA ILI ICC ICC CI input leakage current quiescent supply current VI = VIH or VIL VI = VCC or GND; IO = 0 4.5 4.5 5.5 5.5 5.5 - - - - - - - - - - - - - 0.1 0.55 2.0 40 1.5 10 V V A A mA pF 4.5 4.5 4.4 3.70 - - - - V V 4.5 to 5.5 4.5 to 5.5 2.0 - - - - 0.8 V V VCC (V) MIN. TYP. MAX. UNIT
additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 input capacitance
2004 Jan 21
10
Philips Semiconductors
Product specification
2-input NAND gate
AC CHARACTERISTICS Type 74AHC2G00 GND = 0 V; tr = tf 3.0 ns.
74AHC2G00; 74AHCT2G00
TEST CONDITIONS SYMBOL Tamb = 25 C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 Tamb = -40 to +85 C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 Tamb = -40 to +125 C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 3.0 to 3.6 4.5 to 5.5 3.0 to 3.6 4.5 to 5.5 Notes 1. Typical values are measured at VCC = 3.3 V. 2. Typical values are measured at VCC = 5.0 V. 1.0 1.0 1.0 1.0 - - - - 10.5 7.0 14.5 9.5 ns ns ns ns 3.0 to 3.6 4.5 to 5.5 3.0 to 3.6 4.5 to 5.5 1.0 1.0 1.0 1.0 - - - - 9.5 6.5 13.0 8.5 ns ns ns ns 3.0 to 3.6 4.5 to 5.5 3.0 to 3.6 4.5 to 5.5 - - - - 4.5(1) 3.5(2) 6.5(1) 4.9(2) 7.9 5.5 11.4 7.5 ns ns ns ns PARAMETER WAVEFORMS CL (pF) VCC (V) MIN. TYP. MAX. UNIT
2004 Jan 21
11
Philips Semiconductors
Product specification
2-input NAND gate
Type 74AHCT2G00 GND = 0 V; tr = tf 3.0 ns.
74AHC2G00; 74AHCT2G00
TEST CONDITIONS SYMBOL Tamb = 25 C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 4.5 to 5.5 4.5 to 5.5 1.0 1.0 3.6(1) 5.0(1) - - - - 6.2 7.9 ns ns PARAMETER WAVEFORMS CL (pF) VCC (V) MIN. TYP. MAX. UNIT
Tamb = -40 to +85 C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 4.5 to 5.5 4.5 to 5.5 1.0 1.0 7.1 9.0 ns ns
Tamb = -40 to +125 C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 4.5 to 5.5 4.5 to 5.5 1.0 1.0 8.0 10.0 ns ns
Note 1. Typical values are measured at VCC = 5.0 V.
2004 Jan 21
12
Philips Semiconductors
Product specification
2-input NAND gate
AC WAVEFORMS
74AHC2G00; 74AHCT2G00
handbook, halfpage
nA, nB input
VM
tPHL
tPLH
nY output
VM
MNA213
FAMILY AHC2G00 AHCT2G00
VM INPUT 1.5 V
VM OUTPUT 50% VCC
50% VCC 50% VCC
Fig.5 The inputs (nA and nB) to output (nY) propagation delays.
handbook, halfpage
VCC VI D.U.T. RT CL
MNA101
PULSE GENERATOR
VO
FAMILY AHC2G00 AHCT2G00
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (See "AC characteristics" for the value). RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator.
Fig.6 Load circuitry for switching times.
2004 Jan 21
13
Philips Semiconductors
Product specification
2-input NAND gate
PACKAGE OUTLINES
74AHC2G00; 74AHCT2G00
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
2004 Jan 21
14
Philips Semiconductors
Product specification
2-input NAND gate
74AHC2G00; 74AHCT2G00
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
2004 Jan 21
15
Philips Semiconductors
Product specification
2-input NAND gate
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
74AHC2G00; 74AHCT2G00
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Jan 21
16
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R44/01/pp17
Date of release: 2004
Jan 21
Document order number:
9397 750 12474

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